// SPDX-License-Identifier: GPL-2.0
/*
 * horizon pinmux core definitions
 * Copyright (C) 2022 D-Robotics Holdings Co., Ltd.
 */

#include <common.h>
#include <dm.h>
#include <dm/pinctrl.h>
#include <dt-bindings/pinctrl/horizon-hsio-pinfunc.h>

#include "common.h"

/* The bitfield of each pin in schmitter trigger register */
#define ST_HSIO_ENET_RX_CLK  BIT(0)
#define ST_HSIO_ENET_MDIO    BIT(16)
#define ST_HSIO_ENET_MDC     BIT(24)
#define ST_HSIO_ENET_RXD_0   BIT(0)
#define ST_HSIO_ENET_RXD_1   BIT(8)
#define ST_HSIO_ENET_RXD_2   BIT(16)
#define ST_HSIO_ENET_RXD_3   BIT(24)
#define ST_HSIO_ENET_TXD_0   BIT(0)
#define ST_HSIO_ENET_TXD_1   BIT(8)
#define ST_HSIO_ENET_TXD_2   BIT(16)
#define ST_HSIO_ENET_TXD_3   BIT(24)
#define ST_HSIO_ENET_RXDV    BIT(0)
#define ST_HSIO_ENET_TX_CLK  BIT(8)
#define ST_HSIO_ENET_TXEN    BIT(16)
#define ST_HSIO_ENET_PHY_CLK BIT(0)

#define ST_HSIO_QSPI_DATA0 BIT(0)
#define ST_HSIO_QSPI_DATA1 BIT(8)
#define ST_HSIO_QSPI_DATA2 BIT(16)
#define ST_HSIO_QSPI_DATA3 BIT(24)
#define ST_HSIO_QSPI_SCLK  BIT(0)
#define ST_HSIO_QSPI_SSN0  BIT(8)
#define ST_HSIO_QSPI_SSN1  BIT(16)

#define ST_HSIO_SD_DATA0 BIT(0)
#define ST_HSIO_SD_DATA1 BIT(8)
#define ST_HSIO_SD_DATA2 BIT(16)
#define ST_HSIO_SD_DATA3 BIT(24)
#define ST_HSIO_SD_WP	 BIT(0)
#define ST_HSIO_SD_CMD	 BIT(8)
#define ST_HSIO_SD_CLK	 BIT(16)
#define ST_HSIO_SD_CDN	 BIT(24)

#define ST_HSIO_SDIO_DATA0 BIT(0)
#define ST_HSIO_SDIO_DATA1 BIT(8)
#define ST_HSIO_SDIO_DATA2 BIT(16)
#define ST_HSIO_SDIO_DATA3 BIT(24)
#define ST_HSIO_SDIO_WP	   BIT(0)
#define ST_HSIO_SDIO_CMD   BIT(8)
#define ST_HSIO_SDIO_CLK   BIT(16)
#define ST_HSIO_SDIO_CDN   BIT(24)

#define ST_HSIO_EMMC_DATA0 BIT(0)
#define ST_HSIO_EMMC_DATA1 BIT(8)
#define ST_HSIO_EMMC_DATA2 BIT(16)
#define ST_HSIO_EMMC_DATA3 BIT(24)
#define ST_HSIO_EMMC_DATA4 BIT(0)
#define ST_HSIO_EMMC_DATA5 BIT(8)
#define ST_HSIO_EMMC_DATA6 BIT(16)
#define ST_HSIO_EMMC_DATA7 BIT(24)
#define ST_HSIO_EMMC_CLK   BIT(0)
#define ST_HSIO_EMMC_RSTN  BIT(8)
#define ST_HSIO_EMMC_CMD   BIT(16)

/* Driving selector offset */
#define DS_HSIO_ENET_RX_CLK  1
#define DS_HSIO_ENET_MDIO    17
#define DS_HSIO_ENET_MDC     25
#define DS_HSIO_ENET_RXD_0   1
#define DS_HSIO_ENET_RXD_1   9
#define DS_HSIO_ENET_RXD_2   17
#define DS_HSIO_ENET_RXD_3   25
#define DS_HSIO_ENET_TXD_0   1
#define DS_HSIO_ENET_TXD_1   9
#define DS_HSIO_ENET_TXD_2   17
#define DS_HSIO_ENET_TXD_3   25
#define DS_HSIO_ENET_RXDV    1
#define DS_HSIO_ENET_TX_CLK  9
#define DS_HSIO_ENET_TXEN    17
#define DS_HSIO_ENET_PHY_CLK 1

#define DS_HSIO_QSPI_DATA0 1
#define DS_HSIO_QSPI_DATA1 9
#define DS_HSIO_QSPI_DATA2 17
#define DS_HSIO_QSPI_DATA3 25
#define DS_HSIO_QSPI_SCLK  1
#define DS_HSIO_QSPI_SSN0  9
#define DS_HSIO_QSPI_SSN1  17

#define DS_HSIO_SD_DATA0 1
#define DS_HSIO_SD_DATA1 9
#define DS_HSIO_SD_DATA2 17
#define DS_HSIO_SD_DATA3 25
#define DS_HSIO_SD_WP	 1
#define DS_HSIO_SD_CMD	 9
#define DS_HSIO_SD_CLK	 17
#define DS_HSIO_SD_CDN	 25

#define DS_HSIO_SDIO_DATA0 1
#define DS_HSIO_SDIO_DATA1 9
#define DS_HSIO_SDIO_DATA2 17
#define DS_HSIO_SDIO_DATA3 25
#define DS_HSIO_SDIO_WP	   1
#define DS_HSIO_SDIO_CMD   9
#define DS_HSIO_SDIO_CLK   17
#define DS_HSIO_SDIO_CDN   25

#define DS_HSIO_EMMC_DATA0 1
#define DS_HSIO_EMMC_DATA1 9
#define DS_HSIO_EMMC_DATA2 17
#define DS_HSIO_EMMC_DATA3 25
#define DS_HSIO_EMMC_DATA4 1
#define DS_HSIO_EMMC_DATA5 9
#define DS_HSIO_EMMC_DATA6 17
#define DS_HSIO_EMMC_DATA7 25
#define DS_HSIO_EMMC_CLK   1
#define DS_HSIO_EMMC_RSTN  9
#define DS_HSIO_EMMC_CMD   17

/* The bitfield of each pin in pull down enable register */
#define PD_HSIO_ENET_RX_CLK  BIT(5)
#define PD_HSIO_ENET_MDIO    BIT(21)
#define PD_HSIO_ENET_MDC     BIT(29)
#define PD_HSIO_ENET_RXD_0   BIT(5)
#define PD_HSIO_ENET_RXD_1   BIT(13)
#define PD_HSIO_ENET_RXD_2   BIT(21)
#define PD_HSIO_ENET_RXD_3   BIT(29)
#define PD_HSIO_ENET_TXD_0   BIT(5)
#define PD_HSIO_ENET_TXD_1   BIT(13)
#define PD_HSIO_ENET_TXD_2   BIT(21)
#define PD_HSIO_ENET_TXD_3   BIT(29)
#define PD_HSIO_ENET_RXDV    BIT(5)
#define PD_HSIO_ENET_TX_CLK  BIT(13)
#define PD_HSIO_ENET_TXEN    BIT(21)
#define PD_HSIO_ENET_PHY_CLK BIT(5)

#define PD_HSIO_SD_DATA0 BIT(5)
#define PD_HSIO_SD_DATA1 BIT(13)
#define PD_HSIO_SD_DATA2 BIT(21)
#define PD_HSIO_SD_DATA3 BIT(29)
#define PD_HSIO_SD_WP	 BIT(5)
#define PD_HSIO_SD_CMD	 BIT(13)
#define PD_HSIO_SD_CLK	 BIT(21)
#define PD_HSIO_SD_CDN	 BIT(29)

#define PD_HSIO_SDIO_DATA0 BIT(5)
#define PD_HSIO_SDIO_DATA1 BIT(13)
#define PD_HSIO_SDIO_DATA2 BIT(21)
#define PD_HSIO_SDIO_DATA3 BIT(29)
#define PD_HSIO_SDIO_WP	   BIT(5)
#define PD_HSIO_SDIO_CMD   BIT(13)
#define PD_HSIO_SDIO_CLK   BIT(21)
#define PD_HSIO_SDIO_CDN   BIT(29)

#define PD_HSIO_EMMC_DATA0 BIT(5)
#define PD_HSIO_EMMC_DATA1 BIT(13)
#define PD_HSIO_EMMC_DATA2 BIT(21)
#define PD_HSIO_EMMC_DATA3 BIT(29)
#define PD_HSIO_EMMC_DATA4 BIT(5)
#define PD_HSIO_EMMC_DATA5 BIT(13)
#define PD_HSIO_EMMC_DATA6 BIT(21)
#define PD_HSIO_EMMC_DATA7 BIT(29)
#define PD_HSIO_EMMC_CLK   BIT(5)
#define PD_HSIO_EMMC_RSTN  BIT(13)
#define PD_HSIO_EMMC_CMD   BIT(21)

/* The bitfield of each pin in pull up enable register */
#define PU_HSIO_ENET_RX_CLK  BIT(6)
#define PU_HSIO_ENET_MDIO    BIT(22)
#define PU_HSIO_ENET_MDC     BIT(30)
#define PU_HSIO_ENET_RXD_0   BIT(6)
#define PU_HSIO_ENET_RXD_1   BIT(14)
#define PU_HSIO_ENET_RXD_2   BIT(22)
#define PU_HSIO_ENET_RXD_3   BIT(30)
#define PU_HSIO_ENET_TXD_0   BIT(6)
#define PU_HSIO_ENET_TXD_1   BIT(14)
#define PU_HSIO_ENET_TXD_2   BIT(22)
#define PU_HSIO_ENET_TXD_3   BIT(30)
#define PU_HSIO_ENET_RXDV    BIT(6)
#define PU_HSIO_ENET_TX_CLK  BIT(14)
#define PU_HSIO_ENET_TXEN    BIT(22)
#define PU_HSIO_ENET_PHY_CLK BIT(6)

#define PU_HSIO_SD_DATA0 BIT(6)
#define PU_HSIO_SD_DATA1 BIT(14)
#define PU_HSIO_SD_DATA2 BIT(22)
#define PU_HSIO_SD_DATA3 BIT(30)
#define PU_HSIO_SD_WP	 BIT(6)
#define PU_HSIO_SD_CMD	 BIT(14)
#define PU_HSIO_SD_CLK	 BIT(22)
#define PU_HSIO_SD_CDN	 BIT(30)

#define PU_HSIO_SDIO_DATA0 BIT(6)
#define PU_HSIO_SDIO_DATA1 BIT(14)
#define PU_HSIO_SDIO_DATA2 BIT(22)
#define PU_HSIO_SDIO_DATA3 BIT(30)
#define PU_HSIO_SDIO_WP	   BIT(6)
#define PU_HSIO_SDIO_CMD   BIT(14)
#define PU_HSIO_SDIO_CLK   BIT(22)
#define PU_HSIO_SDIO_CDN   BIT(30)

#define PU_HSIO_EMMC_DATA0 BIT(6)
#define PU_HSIO_EMMC_DATA1 BIT(14)
#define PU_HSIO_EMMC_DATA2 BIT(22)
#define PU_HSIO_EMMC_DATA3 BIT(30)
#define PU_HSIO_EMMC_DATA4 BIT(6)
#define PU_HSIO_EMMC_DATA5 BIT(14)
#define PU_HSIO_EMMC_DATA6 BIT(22)
#define PU_HSIO_EMMC_DATA7 BIT(30)
#define PU_HSIO_EMMC_CLK   BIT(6)
#define PU_HSIO_EMMC_RSTN  BIT(14)
#define PU_HSIO_EMMC_CMD   BIT(22)
/* The bitfield of each pin in pull select register */
#define PS_HSIO_QSPI_DATA0 BIT(5)
#define PS_HSIO_QSPI_DATA1 BIT(13)
#define PS_HSIO_QSPI_DATA2 BIT(21)
#define PS_HSIO_QSPI_DATA3 BIT(29)
#define PS_HSIO_QSPI_SCLK  BIT(5)
#define PS_HSIO_QSPI_SSN0  BIT(13)
#define PS_HSIO_QSPI_SSN1  BIT(21)

/* The bitfield of each pin in pull enable register */
#define PE_HSIO_QSPI_DATA0 BIT(6)
#define PE_HSIO_QSPI_DATA1 BIT(14)
#define PE_HSIO_QSPI_DATA2 BIT(22)
#define PE_HSIO_QSPI_DATA3 BIT(30)
#define PE_HSIO_QSPI_SCLK  BIT(6)
#define PE_HSIO_QSPI_SSN0  BIT(14)
#define PE_HSIO_QSPI_SSN1  BIT(22)

/* The bitfield of each pin in mode select register */
#define MS_HSIO_SD   BIT(1)
#define MS_HSIO_SDIO   BIT(1)
#define MS_HSIO_ENET BIT(2)
#define MS_HSIO_EMMC BIT(3)

static const struct horizon_pin_desc horizon_hsio_pins_desc[] = {
	_PIN(HSIO_ENET_RX_CLK, "hsio_enet_rx_clk", HSIO_PINCTRL_0, INVALID_REG_DOMAIN,
	     DS_HSIO_ENET_RX_CLK, INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_ENET_RX_CLK,
	     PD_HSIO_ENET_RX_CLK, ST_HSIO_ENET_RX_CLK, MS_HSIO_ENET),
	_PIN(HSIO_ENET_MDIO, "hsio_enet_mdio", HSIO_PINCTRL_0, INVALID_REG_DOMAIN,
	     DS_HSIO_ENET_MDIO, INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_ENET_MDIO,
	     PD_HSIO_ENET_MDIO, ST_HSIO_ENET_MDIO, MS_HSIO_ENET),
	_PIN(HSIO_ENET_MDC, "hsio_enet_mdc", HSIO_PINCTRL_0, INVALID_REG_DOMAIN, DS_HSIO_ENET_MDC,
	     INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_ENET_MDC, PD_HSIO_ENET_MDC,
	     ST_HSIO_ENET_MDC, MS_HSIO_ENET),
	_PIN(HSIO_ENET_RXD_0, "hsio_enet_rxd_0", HSIO_PINCTRL_1, INVALID_REG_DOMAIN,
	     DS_HSIO_ENET_RXD_0, INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_ENET_RXD_0,
	     PD_HSIO_ENET_RXD_0, ST_HSIO_ENET_RXD_0, MS_HSIO_ENET),
	_PIN(HSIO_ENET_RXD_1, "hsio_enet_rxd_1", HSIO_PINCTRL_1, INVALID_REG_DOMAIN,
	     DS_HSIO_ENET_RXD_1, INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_ENET_RXD_1,
	     PD_HSIO_ENET_RXD_1, ST_HSIO_ENET_RXD_1, MS_HSIO_ENET),
	_PIN(HSIO_ENET_RXD_2, "hsio_enet_rxd_2", HSIO_PINCTRL_1, INVALID_REG_DOMAIN,
	     DS_HSIO_ENET_RXD_2, INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_ENET_RXD_2,
	     PD_HSIO_ENET_RXD_2, ST_HSIO_ENET_RXD_2, MS_HSIO_ENET),
	_PIN(HSIO_ENET_RXD_3, "hsio_enet_rxd_3", HSIO_PINCTRL_1, INVALID_REG_DOMAIN,
	     DS_HSIO_ENET_RXD_3, INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_ENET_RXD_3,
	     PD_HSIO_ENET_RXD_3, ST_HSIO_ENET_RXD_3, MS_HSIO_ENET),
	_PIN(HSIO_ENET_TXD_0, "hsio_enet_txd_0", HSIO_PINCTRL_2, INVALID_REG_DOMAIN,
	     DS_HSIO_ENET_TXD_0, INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_ENET_TXD_0,
	     PD_HSIO_ENET_TXD_0, ST_HSIO_ENET_TXD_0, MS_HSIO_ENET),
	_PIN(HSIO_ENET_TXD_1, "hsio_enet_txd_1", HSIO_PINCTRL_2, INVALID_REG_DOMAIN,
	     DS_HSIO_ENET_TXD_1, INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_ENET_TXD_1,
	     PD_HSIO_ENET_TXD_1, ST_HSIO_ENET_TXD_1, MS_HSIO_ENET),
	_PIN(HSIO_ENET_TXD_2, "hsio_enet_txd_2", HSIO_PINCTRL_2, INVALID_REG_DOMAIN,
	     DS_HSIO_ENET_TXD_2, INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_ENET_TXD_2,
	     PD_HSIO_ENET_TXD_2, ST_HSIO_ENET_TXD_2, MS_HSIO_ENET),
	_PIN(HSIO_ENET_TXD_3, "hsio_enet_txd_3", HSIO_PINCTRL_2, INVALID_REG_DOMAIN,
	     DS_HSIO_ENET_TXD_3, INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_ENET_TXD_3,
	     PD_HSIO_ENET_TXD_3, ST_HSIO_ENET_TXD_3, MS_HSIO_ENET),
	_PIN(HSIO_ENET_RXDV, "hsio_enet_rxdv", HSIO_PINCTRL_3, INVALID_REG_DOMAIN,
	     DS_HSIO_ENET_RXDV, INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_ENET_RXDV,
	     PD_HSIO_ENET_RXDV, ST_HSIO_ENET_RXDV, MS_HSIO_ENET),
	_PIN(HSIO_ENET_TX_CLK, "hsio_enet_tx_clk", HSIO_PINCTRL_3, INVALID_REG_DOMAIN,
	     DS_HSIO_ENET_TX_CLK, INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_ENET_TX_CLK,
	     PD_HSIO_ENET_TX_CLK, ST_HSIO_ENET_TX_CLK, MS_HSIO_ENET),
	_PIN(HSIO_ENET_TXEN, "hsio_enet_txen", HSIO_PINCTRL_3, INVALID_REG_DOMAIN,
	     DS_HSIO_ENET_TXEN, INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_ENET_TXEN,
	     PD_HSIO_ENET_TXEN, ST_HSIO_ENET_TXEN, MS_HSIO_ENET),
	_PIN(HSIO_ENET_PHY_CLK, "hsio_enet_phy_clk", HSIO_PINCTRL_10, INVALID_REG_DOMAIN,
	     DS_HSIO_ENET_PHY_CLK, INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_ENET_PHY_CLK,
	     PD_HSIO_ENET_PHY_CLK, ST_HSIO_ENET_PHY_CLK, MS_HSIO_ENET),
	_PIN(HSIO_QSPI_DATA0, "hsio_qspi_data0", HSIO_PINCTRL_4, INVALID_REG_DOMAIN,
	     DS_HSIO_QSPI_DATA0, PE_HSIO_QSPI_DATA0, PS_HSIO_QSPI_DATA0, INVALID_PULL_BIT,
	     INVALID_PULL_BIT, ST_HSIO_QSPI_DATA0, INVALID_MS_BIT),
	_PIN(HSIO_QSPI_DATA1, "hsio_qspi_data1", HSIO_PINCTRL_4, INVALID_REG_DOMAIN,
	     DS_HSIO_QSPI_DATA1, PE_HSIO_QSPI_DATA1, PS_HSIO_QSPI_DATA1, INVALID_PULL_BIT,
	     INVALID_PULL_BIT, ST_HSIO_QSPI_DATA1, INVALID_MS_BIT),
	_PIN(HSIO_QSPI_DATA2, "hsio_qspi_data2", HSIO_PINCTRL_4, INVALID_REG_DOMAIN,
	     DS_HSIO_QSPI_DATA2, PE_HSIO_QSPI_DATA2, PS_HSIO_QSPI_DATA2, INVALID_PULL_BIT,
	     INVALID_PULL_BIT, ST_HSIO_QSPI_DATA2, INVALID_MS_BIT),
	_PIN(HSIO_QSPI_DATA3, "hsio_qspi_data3", HSIO_PINCTRL_4, INVALID_REG_DOMAIN,
	     DS_HSIO_QSPI_DATA3, PE_HSIO_QSPI_DATA3, PS_HSIO_QSPI_DATA3, INVALID_PULL_BIT,
	     INVALID_PULL_BIT, ST_HSIO_QSPI_DATA3, INVALID_MS_BIT),
	_PIN(HSIO_QSPI_SCLK, "hsio_qspi_sclk", HSIO_PINCTRL_5, INVALID_REG_DOMAIN,
	     DS_HSIO_QSPI_SCLK, PE_HSIO_QSPI_SCLK, PS_HSIO_QSPI_SCLK, INVALID_PULL_BIT,
	     INVALID_PULL_BIT, ST_HSIO_QSPI_SCLK, INVALID_MS_BIT),
	_PIN(HSIO_QSPI_SSN0, "hsio_qspi_ssn0", HSIO_PINCTRL_5, INVALID_REG_DOMAIN,
	     DS_HSIO_QSPI_SSN0, PE_HSIO_QSPI_SSN0, PS_HSIO_QSPI_SSN0, INVALID_PULL_BIT,
	     INVALID_PULL_BIT, ST_HSIO_QSPI_SSN0, INVALID_MS_BIT),
	_PIN(HSIO_QSPI_SSN1, "hsio_qspi_ssn1", HSIO_PINCTRL_5, INVALID_REG_DOMAIN,
	     DS_HSIO_QSPI_SSN1, PE_HSIO_QSPI_SSN1, PS_HSIO_QSPI_SSN1, INVALID_PULL_BIT,
	     INVALID_PULL_BIT, ST_HSIO_QSPI_SSN1, INVALID_MS_BIT),
	_PIN(HSIO_SD_DATA0, "hsio_sd_data0", HSIO_PINCTRL_6, INVALID_REG_DOMAIN, DS_HSIO_SD_DATA0,
	     INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_SD_DATA0, PD_HSIO_SD_DATA0,
	     ST_HSIO_SD_DATA0, MS_HSIO_SD),
	_PIN(HSIO_SD_DATA1, "hsio_sd_data1", HSIO_PINCTRL_6, INVALID_REG_DOMAIN, DS_HSIO_SD_DATA1,
	     INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_SD_DATA1, PD_HSIO_SD_DATA1,
	     ST_HSIO_SD_DATA1, MS_HSIO_SD),
	_PIN(HSIO_SD_DATA2, "hsio_sd_data2", HSIO_PINCTRL_6, INVALID_REG_DOMAIN, DS_HSIO_SD_DATA2,
	     INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_SD_DATA2, PD_HSIO_SD_DATA2,
	     ST_HSIO_SD_DATA2, MS_HSIO_SD),
	_PIN(HSIO_SD_DATA3, "hsio_sd_data3", HSIO_PINCTRL_6, INVALID_REG_DOMAIN, DS_HSIO_SD_DATA3,
	     INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_SD_DATA3, PD_HSIO_SD_DATA3,
	     ST_HSIO_SD_DATA3, MS_HSIO_SD),
	_PIN(HSIO_SD_WP, "hsio_sd_wp", HSIO_PINCTRL_7, INVALID_REG_DOMAIN, DS_HSIO_SD_WP,
	     INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_SD_WP, PD_HSIO_SD_WP, ST_HSIO_SD_WP,
	     MS_HSIO_SD),
	_PIN(HSIO_SD_CMD, "hsio_sd_cmd", HSIO_PINCTRL_7, INVALID_REG_DOMAIN, DS_HSIO_SD_CMD,
	     INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_SD_CMD, PD_HSIO_SD_CMD, ST_HSIO_SD_CMD,
	     MS_HSIO_SD),
	_PIN(HSIO_SD_CLK, "hsio_sd_xlk", HSIO_PINCTRL_7, INVALID_REG_DOMAIN, DS_HSIO_SD_CLK,
	     INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_SD_CLK, PD_HSIO_SD_CLK, ST_HSIO_SD_CLK,
	     MS_HSIO_SD),
	_PIN(HSIO_SD_CDN, "hsio_sd_cdn", HSIO_PINCTRL_7, INVALID_REG_DOMAIN, DS_HSIO_SD_CDN,
	     INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_SD_CDN, PD_HSIO_SD_CDN, ST_HSIO_SD_CDN,
	     MS_HSIO_SD),
	_PIN(HSIO_SDIO_DATA0, "hsio_sdio_data0", HSIO_PINCTRL_8, INVALID_REG_DOMAIN,
	     DS_HSIO_SDIO_DATA0, INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_SDIO_DATA0,
	     PD_HSIO_SDIO_DATA0, ST_HSIO_SDIO_DATA0, MS_HSIO_SDIO),
	_PIN(HSIO_SDIO_DATA1, "hsio_sdio_data1", HSIO_PINCTRL_8, INVALID_REG_DOMAIN,
	     DS_HSIO_SDIO_DATA1, INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_SDIO_DATA1,
	     PD_HSIO_SDIO_DATA1, ST_HSIO_SDIO_DATA1, MS_HSIO_SDIO),
	_PIN(HSIO_SDIO_DATA2, "hsio_sdio_data2", HSIO_PINCTRL_8, INVALID_REG_DOMAIN,
	     DS_HSIO_SDIO_DATA2, INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_SDIO_DATA2,
	     PD_HSIO_SDIO_DATA2, ST_HSIO_SDIO_DATA2, MS_HSIO_SDIO),
	_PIN(HSIO_SDIO_DATA3, "hsio_sdio_data3", HSIO_PINCTRL_8, INVALID_REG_DOMAIN,
	     DS_HSIO_SDIO_DATA3, INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_SDIO_DATA3,
	     PD_HSIO_SDIO_DATA3, ST_HSIO_SDIO_DATA3, MS_HSIO_SDIO),
	_PIN(HSIO_SDIO_WP, "hsio_sdio_wp", HSIO_PINCTRL_9, INVALID_REG_DOMAIN, DS_HSIO_SDIO_WP,
	     INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_SDIO_WP, PD_HSIO_SDIO_WP, ST_HSIO_SDIO_WP,
	     MS_HSIO_SDIO),
	_PIN(HSIO_SDIO_CMD, "hsio_sdio_cmd", HSIO_PINCTRL_9, INVALID_REG_DOMAIN, DS_HSIO_SDIO_CMD,
	     INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_SDIO_CMD, PD_HSIO_SDIO_CMD,
	     ST_HSIO_SDIO_CMD, MS_HSIO_SDIO),
	_PIN(HSIO_SDIO_CLK, "hsio_sdio_xlk", HSIO_PINCTRL_9, INVALID_REG_DOMAIN, DS_HSIO_SDIO_CLK,
	     INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_SDIO_CLK, PD_HSIO_SDIO_CMD,
	     ST_HSIO_SDIO_CLK, MS_HSIO_SDIO),
	_PIN(HSIO_SDIO_CDN, "hsio_sdio_cdn", HSIO_PINCTRL_9, INVALID_REG_DOMAIN, DS_HSIO_SDIO_CDN,
	     INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_SDIO_CDN, PD_HSIO_SDIO_CDN,
	     ST_HSIO_SDIO_CDN, MS_HSIO_SDIO),
	_PIN(HSIO_EMMC_DATA0, "hsio_emmc_data0", HSIO_PINCTRL_13, INVALID_REG_DOMAIN,
	     DS_HSIO_EMMC_DATA0, INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_EMMC_DATA0,
	     PD_HSIO_EMMC_DATA0, ST_HSIO_EMMC_DATA0, MS_HSIO_EMMC),
	_PIN(HSIO_EMMC_DATA1, "hsio_emmc_data1", HSIO_PINCTRL_13, INVALID_REG_DOMAIN,
	     DS_HSIO_EMMC_DATA1, INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_EMMC_DATA1,
	     PD_HSIO_EMMC_DATA1, ST_HSIO_EMMC_DATA1, MS_HSIO_EMMC),
	_PIN(HSIO_EMMC_DATA2, "hsio_emmc_data2", HSIO_PINCTRL_13, INVALID_REG_DOMAIN,
	     DS_HSIO_EMMC_DATA2, INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_EMMC_DATA2,
	     PD_HSIO_EMMC_DATA2, ST_HSIO_EMMC_DATA2, MS_HSIO_EMMC),
	_PIN(HSIO_EMMC_DATA3, "hsio_emmc_data3", HSIO_PINCTRL_13, INVALID_REG_DOMAIN,
	     DS_HSIO_EMMC_DATA3, INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_EMMC_DATA3,
	     PD_HSIO_EMMC_DATA3, ST_HSIO_EMMC_DATA3, MS_HSIO_EMMC),
	_PIN(HSIO_EMMC_DATA4, "hsio_emmc_data4", HSIO_PINCTRL_14, INVALID_REG_DOMAIN,
	     DS_HSIO_EMMC_DATA4, INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_EMMC_DATA4,
	     PD_HSIO_EMMC_DATA4, ST_HSIO_EMMC_DATA4, MS_HSIO_EMMC),
	_PIN(HSIO_EMMC_DATA5, "hsio_emmc_data5", HSIO_PINCTRL_14, INVALID_REG_DOMAIN,
	     DS_HSIO_EMMC_DATA5, INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_EMMC_DATA5,
	     PD_HSIO_EMMC_DATA5, ST_HSIO_EMMC_DATA5, MS_HSIO_EMMC),
	_PIN(HSIO_EMMC_DATA6, "hsio_emmc_data6", HSIO_PINCTRL_14, INVALID_REG_DOMAIN,
	     DS_HSIO_EMMC_DATA6, INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_EMMC_DATA6,
	     PD_HSIO_EMMC_DATA6, ST_HSIO_EMMC_DATA6, MS_HSIO_EMMC),
	_PIN(HSIO_EMMC_DATA7, "hsio_emmc_data7", HSIO_PINCTRL_14, INVALID_REG_DOMAIN,
	     DS_HSIO_EMMC_DATA7, INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_EMMC_DATA7,
	     PD_HSIO_EMMC_DATA7, ST_HSIO_EMMC_DATA7, MS_HSIO_EMMC),
	_PIN(HSIO_EMMC_CLK, "hsio_emmc_clk", HSIO_PINCTRL_15, INVALID_REG_DOMAIN, DS_HSIO_EMMC_CLK,
	     INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_EMMC_CLK, PD_HSIO_EMMC_CLK,
	     ST_HSIO_EMMC_CLK, MS_HSIO_EMMC),
	_PIN(HSIO_EMMC_RSTN, "hsio_emmc_rstn", HSIO_PINCTRL_15, INVALID_REG_DOMAIN,
	     DS_HSIO_EMMC_RSTN, INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_EMMC_RSTN,
	     PD_HSIO_EMMC_RSTN, ST_HSIO_EMMC_RSTN, MS_HSIO_EMMC),
	_PIN(HSIO_EMMC_CMD, "hsio_emmc_cmd", HSIO_PINCTRL_15, INVALID_REG_DOMAIN, DS_HSIO_EMMC_CMD,
	     INVALID_PULL_BIT, INVALID_PULL_BIT, PU_HSIO_EMMC_CMD, PD_HSIO_EMMC_CMD,
	     ST_HSIO_EMMC_CMD, MS_HSIO_EMMC),
};

static const struct horizon_pinctrl_priv horizon_hsio_pinctrl_info = {
	.pins  = horizon_hsio_pins_desc,
	.npins = ARRAY_SIZE(horizon_hsio_pins_desc),
};

static inline int horizon_hsio_pinctrl_set_state(struct udevice *dev, struct udevice *config)
{
	return horizon_pinctrl_set_state(dev, config, &horizon_hsio_pinctrl_info);
}

static inline int horizon_hsio_pinctrl_probe(struct udevice *dev)
{
	return horizon_pinctrl_probe(dev, &horizon_hsio_pinctrl_info);
}

static const struct pinctrl_ops horizon_pinctrl_hsio_ops = {
	.set_state		= horizon_hsio_pinctrl_set_state,
};

static const struct udevice_id horizon_hsio_pinctrl_of_match[] = {
	{
		.compatible = "d-robotics,horizon-hsio-iomuxc",
		.data = (ulong)&horizon_hsio_pinctrl_info,
	},
	{ }
};

U_BOOT_DRIVER(horizon_hsio_pinctrl) = {
	.name		= "horizon_hsio_pinctrl",
	.id		= UCLASS_PINCTRL,
	.of_match	= of_match_ptr(horizon_hsio_pinctrl_of_match),
	.priv_auto	= sizeof(struct horizon_pinctrl_priv),
	.ops		= &horizon_pinctrl_hsio_ops,
	.probe		= horizon_hsio_pinctrl_probe,
};
